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HS-82C55ARH
TM
Data Sheet
August 2000
File Number
3191.2
Radiation Hardened CMOS Programmable Peripheral Interface
The Intersil HS-82C55ARH is a high performance, radiation hardened CMOS version of the industry standard 8255A and is manufactured using a hardened field, self-aligned silicon gate CMOS process. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which are organized into two 8-bit and two 4-bit ports. Each port may be programmed to function as either an input or an output. Additionally, one of the 8-bit ports may be programmed for bidirectional operation, and the two 4-bit ports can be programmed to provide handshaking capabilities. The high performance, radiation hardness, and industry standard configuration of the HS-82C55ARH make it compatible with the HS-80C86RH radiation hardened microprocessor. Static CMOS circuit design insures low operating power. Bus hold circuitry eliminates the need for pull-up resistors. The Intersil hardened field CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95819. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp
Features
* Electrically Screened to SMD # 5962-95819 * QML Qualified per MIL-PRF-38535 Requirements * Radiation Hardened - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . . . . <108 rad(Si)/s - Latch Up Free EPI-CMOS * Low Power Consumption - IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A * Pin Compatible with NMOS 8255A and the Intersil 82C55A * High Speed, No "Wait State" Operation with 5MHz HS-80C86RH * 24 Programmable I/O Pins * Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors * Direct Bit Set/Reset Capability * Enhanced Control Word Read Capability * Hardened Field, Self-Aligned, Junction Isolated CMOS Process * Single 5V Supply * 2.0mA Drive Capability on All I/O Port Outputs * Military Temperature Range . . . . . . . . . . . -55oC to 125oC
Pinout
CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW
PA3 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 PA4 39 PA5 38 PA6 37 PA7 36 WR 35 RESET 34 D0 33 D1 32 D2 31 D3 30 D4 29 D5 28 D6 27 D7 26 VDD 25 PB7 24 PB6 23 PB5 22 PB4 21 PB3
Ordering Information
ORDERING NUMBER 5962R9581901QQC 5962R9581901VQC INTERNAL MKT. NUMBER HS1-82C55ARH-8 HS1-82C55ARH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125
PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HS-82C55ARH Pin Descriptions
SYMBOL PA0-7 PIN NUMBERS 1-4, 37-40 TYPE I/O DESCRIPTION Port A: General purpose I/O Port. Data direction and mode is determined by the contents of the Control Word. Port B: General purpose I/O port. See Port A. Port C (Lower): Combination I/O port and control port associated with Port B. See Port A. Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A. Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are low and as an output when CS and RD are low. VDD: The +5V power supply pin. A 0.1F capacitor between pins 26 and 7 is recommended for decoupling. Ground. Chip Select: A "low" on this input pin enables the communication between the HS-82C55ARH and the CPU. Read: A "low" on this input pin enables the HS-82C55ARH to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the HS-82C55ARH. Write: A "low" on this input pin enables the CPU to write data or control words into the HS-82C55ARH. Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the Least Significant Bits of the address bus (A0 and A1). Reset: A "high" on this input clears the control register and all ports (A, B, C) are set to the input mode. "Bus hold" devices internal to the HS-82C55ARH will hold the I/O port inputs to a logic "1" state with a maximum hold current of 400A.
PB0-7 PC0-3 PC4-7 D0-7
18-25 14-17 10-13 27-34
I/O I/O I/O I/O
VDD
26
I
GND CS
7 6
I I
RD
5
I
WR
36
I
A0 and A1
8, 9
I
Reset
35
I
2
HS-82C55ARH Functional Diagram
POWER SUPPLIES
+5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA7 - PA0
BIDIRECTIONAL DATA BUS D7 - D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4)
I/O PC7 - PC4
GROUP B PORT C LOWER (4)
I/O PC3 - PC0
RD WR A1 A0 RESET
READ/WRITE CONTROL LOGIC
GROUP B CONTROL
GROUP B PORT B (8)
I/O PB7 - PB0
CS
AC Test Circuit
V1
AC Testing Input, Output Waveforms
INPUT R1 2.8V TEST POINT R2 C1 (NOTE) 1.5V 0.4V 1.5V
FROM OUTPUT UNDER TEST
NOTE: AC Testing: All parameters tested as per test circuits. Input rise and fall times are driven at 1V/ns. NOTE: Includes stray and jig capacitance. TEST CONDITIONS DEFINITION TABLE V1 1.7V R1 523 R2 Open C1 150pF
3
HS-82C55ARH Waveforms
TRLRH RD TPVRL INPUT TAVRL CS, A1, A0 TRHAX CS, A1, A0 TRHPX D7 - D0 TAVWL TWHAX WR TDVWH TWHDX TWLWH
D7 - D0 TRLDV TRHDZ
OUTPUT TWHPV
FIGURE 1. MODE 0 (BASIC INPUT)
FIGURE 2. MODE 0 (BASIC OUTPUT)
TWHOL TSLSH STB WR TKLOH IBF TSLIH TRHIL INTR TSHNH RD TSHPX INPUT FROM PERIPHERAL TPVSH OUTPUT TWHPV ACK TKLKH TKHNH INTR TWLNL OBF TRLNL
FIGURE 3. MODE 1 (STROBED INPUT)
FIGURE 4. MODE 1 (STROBED OUTPUT)
DATA FROM CPU TO HS-82C55ARH WR TKLOH OBF TWHOL INTR ACK TSLSH STB TKLKH
A0 - A1, CS TAVWL DATA BUS TDVWH TWHDX WR TWLWH TWHAX
FIGURE 6. WRITE TIMING
IBF TSLIH TKLPV TPVSH PERIPHERAL BUS RD DATA FROM PERIPHERAL TO HS-82C55ARH TKHPX A0 - A1, CS TAVRL TSHPX DATA FROM HS-82C55ARH TO PERIPHERAL TRHIL RD TRHDX DATA FROM HS-82C55ARH TO CPU TAVRL DATA BUS HIGH IMPEDANCE VALID HIGH IMPEDANCE TRLRH TRHAX
FIGURE 5. MODE 2 (BIDIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
FIGURE 7. READ TIMING
4
HS-82C55ARH Burn-In Circuits
PROGRAMMABLE PERIPHERAL INTERFACE
VDD
PROGRAMMABLE PERIPHERAL INTERFACE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 F4 F0 F5 F0 F2 F1 F0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD F7 F3 F4 F6 F5 F0
STATIC CONFIGURATION NOTES: 1. VDD = 6.0V 0.5% 2. IDD <500A 3. TA Min = 125oC NOTES:
DYNAMIC CONFIGURATION 4. VDD = 6.0V 5% for Burn-In 5. VDD = 5.0V 5% for Life Test 6. All resistors are 10k 5% 7. -0.3V VIL 0.8V 8. VDD - 1.0V VIH VDD 9. IDD < 5mA 10. F0 = 10kHz, 50% Duty cycle 11. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 . . . F7 = F6/2 12. TA Min = 125oC
5
HS-82C55ARH Irradiation Circuit
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
1 2 3 4 5 6 7 8 +5.5V 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 +5.5V RD WR A1 A0 RESET CS READ/ WRITE CONTROL LOGIC GROUP B CONTROL GROUP B PORT B (8) I/O PB7PB0 D7D0 BIDIRECTIONAL DATA BUS DATA BUS BUFFER 8-BIT INTERNAL DATA BUS POWER SUPPLIES +5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA7PA0
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)
I/O PC7PC4 I/O PC3PC0
FIGURE 8. BLOCK DIAGRAM DATA BUS BUFFER, READ/WRITE, GROUP A AND B CONTROL LOGIC FUNCTIONS
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfer of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.
Group A and Group B Controls
NOTE: 13. VDD = 5.5V
Functional Description
The HS-82C55ARH is a programmable peripheral interface designed to allow microcomputer systems to control and interface with all types of peripheral devices. It has the ability to generate and respond to all asynchronous handshaking signals necessary to transfer data to and from peripheral devices, and it can also interrupt the processor when a peripheral needs servicing. These capabilities allow the HS-82C55ARH to be used in an unlimited number of applications including EXTERNAL SYSTEM CONTROL, ASYNCHRONOUS DATA TRANSFER, and SYSTEMS MONITORING.
The functional configuration of each port is programmed by the systems software. In essence, the CPU writes a control word to the HS-82C55ARH. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the HS-82C55ARH. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control Logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Control Group - Port A and Port C upper (C7 - C4). Control Group - Port B and Port C lower (C3 - C0).
Ports A, B, C
The HS-82C55ARH contains three 8-bit ports (A, B and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the HS-82C55ARH.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus hold devices are present on Port A. See Figure 9A. One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 9B.
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface the HS-82C55ARH to the system data bus (see Figure 8). Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.
Port B
6
HS-82C55ARH
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs in conjunction with Ports A and B. See Figure 9B.
ADDRESS BUS CONTROL BUS DATA BUS
MASTER RESET
RD CONTROL
RD, WR MODE 0 B
D7 - D0 C
A0 - A1 CS A
INTERNAL DATA IN INTERNAL DATA OUT WR SIGNAL
EXTERNAL PORT A PIN
8 I/O
4 I/O
4 I/O
8 I/O
PB7 - PB0 PC3 - PC0 PC7 - PC4 PA7 - PA0
MODE 1
B
C
A
FIGURE 9A.
8 I/O VDD MASTER RESET P MODE 2 8 I/O
PB7 - PB0 CONTROL CONTROL PA7 - PA0 OR I/O OR I/O
B
C
A
8 I/O INTERNAL DATA IN INTERNAL DATA OUT WR SIGNAL EXTERNAL PORT B, C PIN PB7 - PB0 I/O CONTROL
8
BIDIRECTIONAL
PA7 - PA0
FIGURE 10. BASIC MODE DEFINITIONS AND BUS INTERFACE TABLE 1.
FIGURE 9B. FIGURE 9. I/O PORT CONFIGURATION A1 0 0 1 1 A0 0 1 0 1 RD 0 0 0 0 WR 1 1 1 1 CS 0 0 0 0
INPUT OPERATION (READ) Port A - Data Bus Port B - Data Bus Port C - Data Bus Control Word - Data Bus
Operational Description
Control Word
The data direction and mode of Ports A, B and C are determined by the contents of the Control Word. See Figure 11. The Control Word can be both written and read as shown in Table 1 and 2. During write operations, the function of the Control Word being written is determined by data bit D7. If D7 is low, the data on D0 - D3 will set or reset one of the bits of Port C. See Figure 12. During read Operations, the Control Word will always be in the format illustrated in Figure 11 with Bit D7 high to indicate Control Word Mode Information.
TABLE 2. A1 0 0 1 1 A0 0 1 0 1 RD 1 1 1 1 WR 0 0 0 0 CS 0 0 0 0 OUTPUT OPERATION (WRITE) Data Bus - Port A Data Bus - Port B Data Bus - Port C Data Bus - Control Word
TABLE 3. A1 X A0 X RD X WR X CS 1 DISABLE FUNCTION Data Bus - 3-State
7
HS-82C55ARH
TABLE 3. A1 X A0 X RD 1 WR 1 CS 0 DISABLE FUNCTION Data Bus - 3-State
Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape recorder on an interrupt-driven basis. The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the HS-82C55ARH has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins.
CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 BIT SET/RESET X X X 1 = SET 0 = RESET BIT SELECT 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 B0 1 B1 1 B2
CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1
GROUP A PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2
DON'T CARE
MODE SET FLAG 1 = ACTIVE
BIT SET/RESET FLAG 0 = ACTIVE
FIGURE 11. MODE SET CONTROL WORD FORMAT
Mode Selection
There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the RESET input goes "high", all ports will be set to the input mode with all 24 port lines held at the logic "one" level by internal bus hold devices. After reset, the HS-82C55ARH can remain in the input mode with no additional initialization required. This eliminates the need for pull-up or pull-down resistors in all CMOS designs. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single HS-82C55ARH to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status register, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance: Group B can be programmed in
FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT
Single Bit/Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. See Figure 12. This feature reduces software requirements in control-based applications.
Interrupt Control Functions
When the HS-82C55ARH is programmed to operate in Mode 1 or Mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from Port C, can be inhibited or enable by setting or resetting the associated INTE flip-flop, using the Bit Set/Reset function of Port C. This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. INTE Flip-Flop Definition: (BIT-SET) - INTE is SET - Interrupt enable. (BIT-RESET) - INTE is RESET - Interrupt disable.
NOTE: All mask flip-flops are automatically reset during mode selection and device Reset.
8
HS-82C55ARH Operating Modes
Mode 0 (Basic Input/Output)
This functional configuration provides simple input and output operations for each of the three ports. No handshaking it required, data is simply written to or read from a specific port. Mode 0 Basic Functional Definitions: * Two 8-bit ports and two 4-bit ports * Any port can be input or output * Outputs are latched * Inputs are not latched * 16 different Input/Output configurations possible
TRLRH RD TPVRL INPUT TAVRL CS, A1, A0 TRHAX TRHPX
D7 - D0 TRLDV TRHDX
FIGURE 13. MODE 0 (BASIC INPUT)
TWLWH WR TWHDX TDVWH D7 - D0 TAVWL CS, A1, A0 TWHAX
OUTPUT TWHPV
FIGURE 14. MODE 0 (BASIC OUTPUT)
9
HS-82C55ARH Mode 0 Port Definition
A D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PORT A Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input GROUP A PORT C (UPPER) Output Output Output Output Input Input Input Input Output Output Output Output Input Input Input Input NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PORT B Output Output Input Input Output Output Input Input Output Output Input Input Output Output Input Input GROUP B PORT C (LOWER) Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input
Mode 0 Configurations
CONTROL WORD #0
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
CONTROL WORD #1
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #3
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
10
HS-82C55ARH Mode 0 Configurations
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
(Continued) CONTROL WORD #5
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
CONTROL WORD #4
B
CONTROL WORD #6
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #7
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #9
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
CONTROL WORD #10
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
11
HS-82C55ARH Mode 0 Configurations
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 B C A 4 4 8
(Continued) CONTROL WORD #13
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 1 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
CONTROL WORD #12
B
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 1 0 8 A 4 D7 - D0 C 4 8 PA7 - PA0 PC7 - PC4 D7 - D0 PC3 - PC0 PB7 - PB0 1 0 0 1 1
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 8 A 4 C 4 8 PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0
B
B
Operating Modes
Mode 1 (Strobed Input/Output)
This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or "handshaking" signals. In Mode 1, Port A and Port B use the lines on Port C to generate or accept these "handshaking" signals. Mode 1 Basic Functional Definitions: * Two Groups (Group A and Group B) * Each group contains one 8-bit port and one 4-bit control/data port. * The 8-bit data port can be either input or output. Both inputs and outputs are latched. * The 4-bit port is used for control and status of the 8-bit port.
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the rising edge of STB and reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port.
INTE A
Controlled by Bit Set/Reset of PC4.
INTE B
Controlled by Bit Set/Reset of PC2.
MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1
PC6, 7 1 = INPUT 0 = OUTPUT PA7 - PA0 INTE A PC4 PC5 8 STB A IBF A RD PC3 2 PC6, 7 I/O INTR A PC0 INTR B PB7 - PB0 INTE B PC2 PC1 8 STB B IBF B
Input Control Signal Definition
STB (Strobe Input)
A "low" on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input.
RD
FIGURE 15. MODE 1 INPUT
12
HS-82C55ARH
TSLSH STB
INTE A
Controlled by Bit Set/Reset of PC6.
IBF TSLIH
INTE B
TRLNL TRHIL
Controlled by Bit Set/Reset of PC2.
TWHOL
INTR TSHNH RD TSHPX INPUT FROM PERIPHERAL TPVSH INTR TWLNL OBF WR
TKHOL
FIGURE 16. MODE 1 (STROBED INPUT)
ACK
Output Control Signal Definition
OBF (Output Buffer Full F/F)
The OBF output will go "low" to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF. See Note 1. The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low.
OUTPUT TWHPV
TKLKH TKHNH
FIGURE 18. MODE 1 (STROBED OUTPUT) NOTE: 14. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generate an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF.
ACK (Acknowledge Input)
A "low" on this input informs the HS-82C55ARH that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data. See Note 14.
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
PORT A (STROBED INPUT) PORT B (STROBED OUTPUT) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 0 PORT A (STROBED OUTPUT) PORT B (STROBED INPUT) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 1 1
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set by the rising edge of ACK and reset by the falling edge of WR.
MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 0
PC6, 7 1 = INPUT 0 = OUTPUT PA7 - PA0 PC4 PC5 PC3
PC4, 5 1 = INPUT 0 = OUTPUT PA7 - PA0 PC7 PC6 PC3 2 I/O 8 OBF B ACK B INTR B RD PC4, 5 PB7 - PB0 PC2 PC1 PC0 8 STB B IBF B INTR B I/O
RD
8 STB A IBF A INTR A 2
WR
8 OBF A ACK A INTR A
PC4, 5 1 = INPUT 0 = OUTPUT PA7 - PA0 PC7 INTE A WR PC3 2 PC4, 5 I/O INTR A PC6 8 OBF A ACK A WR PC0 INTR B PB7 - PB0 PC1 INTE B PC2 8 OBF B ACK B WR
PC6, 7 PB7 - PB0 PC1 PC2 PC0
FIGURE 19. COMBINATIONS OF MODE 1 FIGURE 17. MODE 1 OUTPUT
13
HS-82C55ARH Operating Modes
MODE 2 (Strobed Bidirectional Bus I/O)
The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). "Handshaking" signals are provided to maintain proper bus flow discipline similar to MODE 1. Interrupt generation and enable/disable functions are also available. Mode 2 Basic Functional Definitions: * Used in Group A only. * One 8-bit, bidirectional bus port (Port A) and a 5-bit control port (Port C). * Both inputs and outputs are latched. * The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A).
PC3 INTR A 1 0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1/0 1/0 1/0 PC2 - PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT GROUP B MODE 0 = MODE 0 1 = MODE 1
FIGURE 20. MODE CONTROL WORD
PA7- PA0 PC7 INTE 1 PC6
8 OBF A ACK A
Bidirectional Bus I/O Control Signal Definition
INTR (INTERRUPT REQUEST) A high on this output can be used to interrupt the CPU for both input or output operations. INTR will be set either by the rising edge of ACK (INTE1 = 1) or the rising edge of STB (INTE2 = 1). INTR will be reset by the falling edge of WR (if previously set by the rising edge or ACK), the falling edge of RD (if previously set by the rising edge of STB), or the falling edge of WR when immediately following a low RD pulse or the falling edge of RD when immediately following a low WR pulse (if previously set by the rising edges of both ACK and STB).
INTE 2 WR RD
PC7 PC6
STB A IBF A
3 PC2- PC0 I/O
FIGURE 21. MODE 2 (BIDIRECTIONAL)
Output Operations
WR
DATA FROM CPU TO HS-82C55ARH TKHOL OBF TWHOL INTR TKLKH
OBF (OUTPUT BUFFER FULL) The OBF output will go "low" to indicate that the CPU has written data out to Port A. ACK (ACKNOWLEDGE) A "low" on this input enables the three-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (THE INTE FLIP-FLOP ASSOCIATED WITH OBF) Controlled by Bit Set/Reset of PC6.
ACK
TSLSH STB IBF TSLIH TKLPV TKHPX TPVSH PERIPHERAL BUS RD DATA FROM PERIPHERAL TO HS-82C55ARH
Input Operations
STB (STROBE INPUT) A "low" on this input loads data into the input latch. IBF (INPUT BUFFER FULL F/F) A "high" on this output indicates that data has been loaded into the input latch. INTE 2 (THE INTE FLIP-FLOP ASSOCIATED WITH IBF) Controlled by Bit Set/Reset of PC4.
TSHPX DATA FROM HS-82C55ARH TO PERIPHERAL
TRHIL
DATA FROM HS-82C55ARH TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. FIGURE 22. MODE 2 (BIDIRECTIONAL)
14
HS-82C55ARH
MODE DEFINITION SUMMARY MODE 0 IN PA0 AP1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In In In In In In In In In In In In In In In In In OUT Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out IN In In In In In In In In In In In In In In In In INTR B IBF B STB B INTR A STB A IBF A I/O I/O MODE 1 OUT Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out INTR B OBF B ACK B INTR A I/O I/O ACK A OBF A I/O I/O I/O INTR A STB A IBF A ACK A OBF A MODE 2 GROUP A ONLY
Mode 0 or Mode 1 Only
Special Mode Combination Considerations
There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a "Set Mode" command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 25. Through a "Write Port C" command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a "Write Port C" command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to change an interrupt enable flag, the "Set/Reset Port C Bit" command must be used. With a "Set/Reset Port C Bit" command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C fare not affected by a "Set/ Reset Port C Bit" command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the "Set/ Reset Port C Bit" command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 25.
D7 I/O D6 I/O D5
INPUT CONFIGURATION D4 D3 D2 INTEA INTRA INTEB
D1 IBFB
D0 INTRB
IBFA
GROUP A OUTPUT CONFIGURATION D5 D4 D3 D2 I/O I/O INTRA
GROUP B
D7
D6
D1
D0
OBFA INTEA
INTEB OBFB INTRB
GROUP A
GROUP B
FIGURE 23. MODE 1 STATUS WORD FORMAT
D7 OBFA
D6 INTE1
D5 IBFA
D4 INTE2
D3 INTRA
D2 X
D1 X
D0 X
GROUP A NOTE: (Defined by Mode 0 or Mode 1 Selection)
GROUP B
FIGURE 24. MODE 2 STATUS WORD FORMAT
15
HS-82C55ARH
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function.
INTERRUPT ENABLE FLAG INTE B ALTERNATE PORT C PIN SIGNAL (MODE) ACKB (Output Mode 1) or STBB (Input Mode 1) STBA (Input Mode 1 or Mode 2) ACKA (Output Mode 1 or Mode 2)
POSITION PC2
Reading Port C Status (Figures 23 and 24)
In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes 1 or 2, Port C generates or accepts "hand shaking" signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the "status" of each peripheral device and change the program flow accordingly.
INTE A2
PC4
INTE A1
PC6
FIGURE 25. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
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HS-82C55ARH Die Characteristics
DIE DIMENSIONS: 3420m x 4350m x 485m 25m INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kA 1kA Top Metallization: Type: Al/Si Thickness: 11kA 2kA ADDITIONAL INFORMATION: Worst Case Current Density: 7.7 x 104 A/cm2
Metallization Mask Layout
(15) PC1 (14) PC0 (13) PC4 (12) PC5
HS-82C55ARH
(11) PC6 (10) PC7 (7) VSS (6) CS (9) A0 (8) A1
PC2 (16) PC3 (17) PB0 (18) PB1 (19) PB2 (20)
(5) RD (4) PA0 (3) PA1 (2) PA2 (1) PA3
PB3 (21) PB4 (22) PB5 (23) PB6 (24) PB7 (25)
(40) PA4 (39) PA5 (38) PA6 (37) PA7 (36) WR
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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RESET (35)
VDD (26)
D7 (27)
D6 (28)
D5 (29)
D4 (30)
D3 (31)
D2 (32)
D1 (33)
D0 (34)

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